1. Field of the Invention
The present invention relates to a solid-state imaging apparatus, and more particularly to a read circuit in the solid-state imaging apparatus.
2. Description of the Related Art
Solid-state imaging apparatuses have been used in digital cameras in recent years. As typical solid-state imaging apparatuses, a CCD type and an MOS type solid-state imaging apparatuses are cited. An MOS type solid-state imaging apparatus has a pixel unit in which photoelectric conversion elements such as a photodiode are two-dimensionally arranged, a signal accumulating unit which accumulates signals from the pixel unit, and a common signal line (horizontal signal line) for outputting signals of the signal accumulating unit to an outside.
In recent years, in response to increase in the number of pixels of solid-state imaging apparatus, enhancement in speed of signal reading has been demanded. A horizontal scanning unit especially needs to select a number of signals and read the signals as compared with a vertical scanning circuit, and therefore, is required to enhance the speed.
Japanese Patent Application Laid-Open No. 2003-234963 describes a noise reduction technique when signal reading speed in the horizontal scanning unit is enhanced. More specifically, a shift register which configures the horizontal scanning unit is divided into a plurality of partial shift registers. Japanese Patent Application Laid-Open No. 2003-234963 describes the construction in which a shift clock control circuit individually controls supply of the shift clock to a partial shift register for each partial shift register.
Further, the signal reading speed is influenced by the capacity of a common signal line and the reset speed of the common signal line. Reset of the common signal line means setting the potential of the common signal line to a predetermined potential before reading a signal or after reading the signal.
Japanese Patent Application Laid-Open No. H10-191173 describes the construction having a unit for setting the potential of the common output lines to a predetermined potential (first reset unit), and a unit for electrically connecting the common output lines and setting the common output lines at the same potential (second reset unit), in the construction having two-system common output lines.
In Japanese Patent No. 4,054,839, in order to reduce the capacity of the common signal line, a plurality of divided block wirings are included between the signal read circuit and the common signal line. Reset units for resetting the potentials of the block wirings are provided at a plurality of block wirings.
When a plurality of reset units are provided for a common signal transferring unit including a common output line as Japanese Patent Application Laid-Open No. H10-191173 and Japanese Patent No. 4,054,839 in the construction using a block horizontal scanning unit as Japanese Patent Application Laid-Open No. 2003-234963, the image quality may degrade depending on the method of reset operation. The construction having a reset unit for each block wiring, for example, will be described.
When the control pulse supply wiring for controlling the reset unit provided at the block wiring is led from the end of the horizontal scanning unit, the block wiring closer to the end is reset earlier. This is because the time constant of the path to which the control pulse is supplied differs depending on the arrangement of the reset unit. Meanwhile, a switch group for reading a signal from a signal accumulating unit group corresponding to each block wiring receives the pulse from the corresponding block horizontal scanning unit, and reads the signal to the block wiring. The control line which controls each block of the horizontal scanning unit is often arranged to propagate to the left and right from the block horizontal scanning circuit located in the center among the block horizontal scanning units, in order to minimize the delay due to the time constant of the pulse supply path. Accordingly, in the respective block horizontal scanning unit, the one in the center operates the earliest, and the delay amount increases toward those at both ends, so that the time of signal reading differs in each block.
When the signal reading speed is enhanced, the temporal margin of the timing of reading a signal from the signal accumulating unit through a switch and the timing at which the common signal line or the block wiring is reset needs to be decreased. Here, the reason why the margin is required is that if the period in which the signal is read to the block wiring, and the period in which the reset operation of the block wiring is performed overlap each other, the signal to be read which is present in the block wiring is reset. If the coinciding amount differs at each block wiring, the signal read amount differs at each block wiring even when the signal of the same magnitude is read, and thereby, shading occurs to influence the image quality.
In the above described construction, timings of read and reset may differ significantly in the block scanning circuit unit in the center into which a pulse to the switch that reads the signal from the signal accumulating unit is input the earliest, and in the block scanning circuit units at both ends into which the pulses are input the latest. As a result, in order to secure a sufficient temporal margin, extra waiting time is required, and a desired operation speed is not obtained. Alternatively, if the timings are closely set unreasonably, a problem in image quality such as shading may occur.
As an example of providing a plurality of reset units, the example of providing the reset units at a plurality of block wirings is described, but the example is not limited to this, and a similar problem also occurs to the case where a plurality of reset units are provided for the common signal line.
In view of such a problem, the present invention has an object to provide a solid-state imaging apparatus capable of performing a reset operation at a high speed while suppressing image quality degrading by shading.